IONION
Products

Processors built
for the extreme.

Three processor families, one secure foundation, engineered for space and beyond.

Detail of the Kairos die
In development

Kairos

RISC-V embedded HPC processor.

Kairos brings high-performance computing to embedded and space systems. Built around a native network-on-chip, it scales up to 64 processing units and combines advanced security and high-reliability features with full Linux OS support.

64
Processing units, maximum
RVA23
Profile compliant
Linux
Full OS support
  • Native Network-on-Chip design
  • Advanced security features, secure boot and execution validation
  • High reliability features
  • AI instruction and custom accelerator support
Request information
Detail of the Aegis die
High Performance MPU

Aegis

Secure, deterministic, Linux-capable multicore.

Aegis is a complete 32-bit RISC-V system-on-chip for systems that must combine Linux-class software, real-time determinism and security in one part. Up to four cache-coherent cores, each with hardware floating point and bit manipulation, share a coherent memory system and a full peripheral set.

5.6
CoreMark/MHz per core
1–4
Cache-coherent cores
1,780
CoreMark/s, Linux, 4 cores on FPGA
  • Hardware root of trust authenticates every boot
  • In-silicon anti-trojan protection
  • Linux, SDK, FreeRTOS and Zephyr support from day one
  • Tightly coupled AI acceleration for signal processing and inference

Available now as an encrypted SoC core for Xilinx FPGAs. Hardened packaged ASIC in development.

Request the datasheet
Detail of the Astraeus die
Rad-tolerant MCU

Astraeus

Every watt is precious. Every cycle counts.

Astraeus is the first radiation-tolerant microcontroller built on a packet-switched network-on-chip: a low-power 32-bit RISC-V core, fault-tolerant memories and a full peripheral set on a deterministic on-chip mesh, engineered to keep space and critical real-time systems working through upsets on a small power budget.

3.02
CoreMark/MHz
0.745
DMIPS/MHz
ECC
SECDED on every memory
  • Deterministic packet-switched mesh network-on-chip
  • Background scrubbing, selective TMR and FDIR
  • Sleep modes and autonomous clock gating for a small power budget
  • SDK, FreeRTOS port and standard GCC toolchain

Available now as encrypted soft SoC IP for Lattice and Xilinx FPGAs. Packaged ASIC in development.

Request the datasheet
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Let’s build secure silicon for systems that cannot fail.

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